In brief

From advanced chip packaging to silicon photonics, this feature story reviews pivotal developments and partnerships that are continuing to shape innovative solutions for a data-hungry age.

© A*STAR Research

The view beyond Moore

7 Jul 2023

With its long-standing expertise and working partnerships, A*STAR continues pushing forward with chip technologies beyond the transistor scaling paradigm.

We live in the age of the integrated circuit (IC). Nearly 70 years after engineers first successfully embedded electronic systems into flat, two-dimensional (2D) ‘chips’ of semiconductive silicon, ICs have revolutionised our lives, putting computers into our hands, homes, workplaces and cities.

Since their invention, ICs have grown exponentially more powerful, energy-efficient, compact and affordable. In 1975, Intel co-founder Gordon Moore predicted the number of transistors per IC would double every 18 months. ‘Moore’s Law’ held for decades: in 1969, the Apollo 11 landed on the Moon using 30-kg computers with 17,000 transistors, each device worth today’s USD$1.5 million. By 2022, Apple’s USD$1,000 smartphones would hold chips with 16 billion transistors; handheld devices powerful enough to guide millions of Apollos, at a significantly reduced cost.

But scaling down has its limits; the rate thereof would slow down by the mid-2000s. “The smallest transistors today are measured in nanometres,” said Ping Koy Lam, A*STAR Chief Quantum Scientist. “The closer they get to the atomic level, the harder it is to keep their behaviour consistent. Atoms don’t obey macroscopic physics.”

Compounding the physical limits of Moore’s Law are economic ones. While downscaling was once a cost-effective way to enhance ICs, it now calls for increasingly complex and pricy processes. In 2020, McKinsey & Company reported that building a facility with 5 nm production lines cost roughly USD$5.4 billion; three times more than a 10 nm facility. Yet with the rise of technologies like artificial intelligence (AI), the Internet of Things (IoT) and high-speed telecommunications, demand for computing power is only set to accelerate.

To meet that demand, A*STAR research institutes such as the Institute of Microelectronics (IME) are looking beyond Moore’s Law for the future of chips. “There are still decades of growth to pursue in IC capabilities,” said Yee Chia Yeo, Assistant Chief Executive (Designate) of the A*STAR Innovation and Enterprise (I&E) Division “While many technical challenges lie ahead, IME has ideas and solutions to advance much further. A key direction is ‘More than Moore’ (MtM): the integration of new functionalities that enhance IC performance, on top of transistor scaling.”

IME aims to facilitate advanced MtM technology development and commercialisation. “Since 1991, we’ve focused on high-impact R&D for the global semiconductor industry,” said Terence Gan, IME Executive Director. “Through strategic partnerships and tech advances, IME aims to push boundaries in this field to drive innovation and bring cutting-edge solutions to the market.”


Advanced packaging is a key area of MtM innovation. Where conventional packaging aims to protect ICs from damage, advanced packaging aims to improve IC performance through how its components are connected and assembled; not just in two dimensions, but three.

“IME’s commitment to MtM is exemplified by our established advanced packaging line with High-Density Fan-Out Wafer Level Packaging (HD-FOWLP), 2.5D and 3D IC integration, and wafer-to-wafer and chip-to-wafer hybrid bonding capabilities,” said Gan. “This line has attracted R&D collaborations from various companies including integrated device manufacturers, fabless semiconductor companies, wafer foundries, outsourced semiconductor assembly and test providers, as well as materials suppliers.”

IME has a long history of collaborative research in chip packaging and taps into the strengths of other A*STAR research institutes such as the Institute of High Performance Computing (IHPC), the Institute for Infocomm Research (I2R), the Singapore Institute of Manufacturing Technology (SIMTech) and the Institute of Materials Research and Engineering (IMRE).

Beyond A*STAR, IME works closely with local and international universities such as the National University of Singapore (NUS), Nanyang Technological University (NTU), the Singapore University of Technology and Design (SUTD) and the University of Michigan, US. Through industry consortia, IME also partners with local and international industry players, starting with the first Electronic Packaging Research Consortium in 1995.

While initially focused on Moore’s Law-adjacent, single-chip packaging technologies such as flip chip, wire bonding, ball grid array (BGA) and copper/low-k, research soon shifted to MtM multi-chip approaches. What if, instead of increasing the number of transistors within an IC, you could package multiple ICs to act in concert?

“When IC technology nodes were around 40 to 28 nm, we started focusing on developing advanced stacking methods for 2.5D and 3D IC designs,” said Tai Chong Chai, a Principal Research Engineer at IME since 1993.

A breakthrough method that IME would delve into was the through-silicon via (TSV). Rather than using solder bumps or wire bonding to make electrical connections (interconnects) between two ICs, vertical channels could be directly bored through them. These would allow multiple ICs to be stacked vertically and assembled in three dimensions, with TSVs linking them as a single, more powerful device.

“We were one of the earliest research groups in the world to work on TSVs, forming our first TSV consortium in 2005,” said Xiaowu Zhang, a Senior Scientist II at IME. “We had the advantage of silicon etching capabilities and expertise in microelectromechanical systems (MEMS) that helped us with fabrication and testing.”

IME’s TSV capabilities would soon catch the attention of US semiconductor equipment manufacturer Applied Materials, which joined hands with IME in 2011 to set up the Centre of Excellence in Advanced Packaging. The joint laboratory, focused on wafer-level packaging (WLP), would be the first of several established with industry partners to develop further MtM technologies.

With end-to-end R&D and pilot production lines established, IME’s work would rapidly evolve over the next decade from enhancing MtM-related processes to developing a host of specialised, application-driven IC technology platforms.


Apart from advanced stacking, another paradigm in MtM tech is the idea of heterogenous integration (HI). By fabricating and assembling a system of multiple, separately manufactured ICs and other components into a shared substrate, their functionality can be boosted for specific uses. For example, a multi-chip module designed for a mobile phone has a different set of ICs from a module designed for a self-driving vehicle.

“The benefit of the system-in-package (SiP), rather than the system-on-chip (SoC), is its modularity and versatility,” said Chai. “You can integrate chips or chiplets from different technology nodes, or radio frequency (RF) chips, sensor chips, and even MEMS.”

IME’s Advanced Packaging group has developed deep capabilities in the design, fabrication and assembly of various cutting-edge HI technologies. These technologies aren’t discrete; they can be combined to create customised solutions for various industry demands.

“Our advanced packaging line has enabled the realisation of novel IC packages for the mobility, IoT, power electronics and millimetre-wave (mmWave) markets,” said Gan. “Through our industry-grade equipment, intellectual property portfolio, end-to-end R&D and pilot production capabilities, we give innovators the necessary support to experiment, prototype and manufacture in small volumes.”

Some recent industry solutions developed at IME include 3D integration of different RF components such as filters, low-noise amplifiers or RF MEMS; 3D integration of piezoelectric micromachined ultrasonic transducers and multiple application-specific IC (ASIC) chips; silicon carbide interposers for high heat dissipation; and co-packaging of electronic and photonic ICs using FOWLP.

In 2021, IME’s HI capabilities would lead to a consortium with industry partners Asahi Kasei, GlobalFoundries, Qorvo and Toray to develop high-density SiP with miniaturised RF front-end modules for 5G applications.

Applied Materials continues to be a key partner in IME’s advanced packaging R&D, with both parties recently signing an agreement for a five-year extension to their research collaboration. The partnership’s new phase will invest an estimated S$280 million to accelerate materials, equipment and process solutions for hybrid bonding and other 3D HI technologies.


With IME’s portfolio of MtM technologies, customised solutions often walk a tightrope between boosting computing power and the practicalities of production. “We can create novel processes, but if they’re not feasible, reliable or cost-effective, the industry won’t adopt them,” said Teck Guan Lim, a Senior Scientist in IME’s SiP group.

Three main HI platforms at IME include:

An advanced form of WLP where silicon wafers are diced into individual chips, then placed on a carrier, where they are overmolded and reconstructed into larger dies or modules with multiple layers of redistribution layers (RDLs) to electrically connect multiple chips. A lower-cost solution than 2.5D packaging, FOWLP’s applications include 5G/6G RF on mobile phones, Antenna-in-Package (AiP), automotive radar, augmented and virtual reality, and gesture sensors.

2.5D integration
The placement of IC dies side-by-side on a silicon interposer to approximate the benefits of an SoC. More powerful than FOWLP but more cost-effective than SoCs, 2.5D applications include high performance computing (HPC), network switches and network routers.

3D integration
The vertical stacking of IC dies to provide a shorter (and hence faster) interconnection. 3D integration can be done wafer-to-wafer or chip-to-wafer and is used in HPC, AI accelerators and other applications that benefit from higher speed and small footprints.


One more avenue of MtM research is the integration of photonic components within silicon ICs. Where electronic networks communicate with electric particles (electrons and holes), their photonic counterparts use light particles (photons).

“Compared to electrons and holes, photons offer several advantages including higher bandwidth, lower power consumption and an immunity to electromagnetic interference,” said Jason Png, Director of IHPC’s Electronics and Photonics Department. “Silicon photonics could lead to more efficient, versatile, and high-performance microelectronics systems through an approach outside transistor scaling.”

Using AI-powered modelling and simulation, coupled with optimisation techniques, IHPC has developed a library of passive and active devices to manipulate photons within circuits and interpret optical data into electronic forms. “These devices are capable of meeting high-performance requirements for low-loss, compact footprints and high speeds,” said Png.

Png added that some of this library’s more promising components have been experimentally validated by other A*STAR research institutes such as IME and IMRE; local educational institutions such as NTU, NUS and SUTD; as well as overseas collaborators.

With potential data transfer rates of 100 Gbps or more, photonics MtM might be a prime solution for fields that need higher-speed data transmission such as data centres, telecommunications and HPC. “Integrating optical interconnects in semiconductor packaging could boost chip-to-chip data transmission rates,” said Lim. “We are working on chip-to-chip communications using interposer waveguides.”

To date, silicon photonics development at IME has led to two spinoffs: Rain Tree Photonics, a developer of high-speed optical interconnects for data centre applications, and Advanced Micro Foundry, a dedicated silicon photonics foundry for innovative manufacturing solutions.


Apart from its R&D and pilot production capabilities, IME also supports ecosystem development initiatives to train the next generation of researchers in advanced IC technologies.

“To develop and inspire future semiconductor leaders, we partner with the Singapore Semiconductor Industry Association (SSIA) on its talent development and outreach programmes,” said Gan. “We also encourage A*STAR talents to share their expertise and learn from global networking events, take advantage of sponsorships to pursue engineering doctorates and participate in SSIA’s leadership development programmes.”

Through its collaborations, educational initiatives, staff development programmes and sponsorships, IME remains dedicated to nurturing talent, fostering innovation and advancing the semiconductor industry in Singapore and beyond. “We strive to build a talented pool of professionals who can drive innovation, lead teams and contribute to the growth and competitiveness of the industry,” Gan added.

“As Singapore’s leading public agency for the advancement of impactful science, A*STAR looks forward to attracting new talents and working with new partners in academia and industry to bring MtM to greater heights,” said Yeo.

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This article was made for A*STAR Research by Wildtype Media Group