© iStockphoto.com/Eduardo Antonio Fuentes
The major source of electronic signal noise in printed circuit boards is not, as one might expect, active electronic components like transistors or diodes, but rather the network of wires responsible for powering these active components.
Although numerical models for printed circuit power distribution networks exist, they are limited in the geometries that they can handle, and are often computationally intensive. This makes it challenging for engineers to design circuits in a way that minimizes noise. Xing-Chang Wei and Er-Ping Li from the A*STAR Institute of High Performance Computing have now developed a more efficient way of calculating the electrical signal noise caused by this power distribution network.
The power distribution network in a multilayered printed circuit consists of multiple patterned planes of wires, called signal traces, and power and ground planes. Holes, or ‘vias’, through the multilayered board connect the signal traces to the ground and power planes, and also to other planar layers patterned with circuits. Current fluctuations flowing through this complex network of signal traces and the compensating currents flowing in the ground and power planes can create crosstalk between different areas of the circuit, resulting in noise that interferes with the processing of real data. This noise is particularly problematic in high-frequency and high-power circuits.
Wei and Li had previously calculated this noise by modelling the ground planes, signal traces and vias with equivalent circuit elements with well-understood behavior. These elements included distributed resistances, capacitors, inductors and one-dimensional transmission lines. This modeling approach could only be applied, however, to networks with a single pair of ground and power planes.
In the present work, the researchers extended this technique to handle multilayered power distribution networks by constructing equivalent circuits for different portions of the network, one at a time. These circuit models were then cascaded together to describe the entire system. The researchers also took into account interactions between vias by including additional capacitors and inductors. However, when the horizontal distance between vias was greater than three times the vertical distance between the relevant ground and power planes, these interactions could be ignored.
The model was compared against a commercially available simulator, called HFSS, that described the printed circuit using a three-dimensional finite element mesh, and was found to produce accurate results in about one tenth of the computation time. The researchers achieved this substantial boost in computational efficiency by decomposing the three-dimensional problem into a series of simpler two-, one- and zero-dimensional problems.
The A*STAR-affiliated researchers contributing to this research are from the Institute of High Performance Computing.
